It is generally known to interconnect two semiconductor devices, one serving for data processing and the other, containing a memory array, serving for data storage. In most common systems, the interconnection is via a bus to which also other devices, as well as multiple memory devices, are connected. Each device is usually implemented as a die, mounted in a suitable package. Certain class types of memory devices, such as flash memory, static random-access memory (SRAM) and electrically erasable programmable read-only memory (EEPROM—implemented also in flash technology), have special structures and characteristics, including moderate operational speed, and, on the other hand, need to be very frequently and readily accessible by the processing device. For these reasons memory devices of such classes are often directly connected, possible via an exclusive bus, to the processing device; often they are also packaged together, in a stacked manner, whereby the interconnecting lines become very short. In effect, this arrangement creates a pair of interactive dies. Because of the special structure and characteristics of the memory device, the mechanical and electrical structure of the interconnection and the protocols governing the interface between the devices are, in prior art, custom designed for the particular pair; moreover, the circuit layout of the processing device is often designed so as to place connecting pads at locations that enable connection to the particular memory device. Thus, in general, prior art requires, for any given type of processing device, a different design of the mechanical and electrical interface, as well as of the processing die's circuit layout, for each different type of memory device. Such a set of interfaces, moreover, would generally, vary among different types of processing device. Furthermore, the characteristics of each memory device to be connected need to be stored in the processing device. Connecting buses of prior art are also characterized by having separate lines for addresses and for data, and/or separate lines for inflow and outflow (relative to the main device). Additionally, interfaces of prior art are designed for only a limited number of bus widths and memory status and control signals are conveyed inefficiently. Moreover, interfaces of prior art do not automatically enable simultaneous access to the memory by a plurality of processes (multiple streams) and generally do not support timing of the memory device based on the clock signal of a synchronous bus.
There is, thus, a need for a standard interface between a processing (or main) device and a memory device that is suitable for a wide range of memory device types, as well as of main device types and that will enable coupling of a main device to a variety of memory devices with relatively minor modifications to its hardware and software. Such a standard interface need also enable efficient data communication between the devices and use a minimal number of connecting lines, while maintaining flexibility in the bus width. There may also be a need for the standard interface to enable simultaneous access to the memory by a plurality of processes and/or to support timing of the memory device based on the clock signal of the synchronous bus. Optionally there may also be a need for the standard interface to connect a plurality of memory devices to a main device, possibly all packaged in a stack.
A list, with brief descriptions, of related prior art follows.
U.S. Pat. No. 5,761,456, to Titus, et al., discloses a processor device and method for booting a programmable apparatus having a signal bus having a selectable bus width. The processor device includes a microprocessor, a configurable bus interface for coupling the microprocessor to the signal bus, and a first memory. The first memory includes a bus sizing code for instructing the microprocessor for reading initial data from a pre-determined address of a second memory and configuring the bus interface to the bus width that has been selected.
U.S. Pat. No. 6,016,270, to Thummalapally, et al., discloses a flash memory architecture that relies on a single, time-shared address bus to enable a read operation to be performed simultaneously with an algorithm operation when the read operation is targeted for a memory cell block that is not currently tagged for an algorithm operation. After a read address has been latched into the array block selected for the read operation, the address bus is “free” for the remainder of the read operation cycle. During this free time, the address bus can be used for algorithm operations to load the counter address into an active tagged block in the array. Separate global data I/O lines are provided to facilitate simultaneous read and algorithm operations.
U.S. Pat. No. 6,235,554, to Akram, et al., discloses a stackable chip scale semiconductor package and a method for fabricating the package. The package includes a substrate having a die mounting site wherein a semiconductor die is mounted. The package also includes first contacts formed on a first surface of the substrate, and second contacts formed on an opposing second surface of the substrate. Conductive vias in the substrate electrically connect the first contacts to the second contacts. In addition, the first contacts and the second contacts have a mating configuration, such that a second package can be stacked on and electrically connected to the package.
U.S. Pat. No. 6,298,426, to Ajanovic, discloses a memory controller for use with a memory sub-system selected to have one of multiple memory organizations. The memory controller includes output drivers connected to output pins, the output drivers being programmable to have one of multiple output characteristics. The memory controller also includes a configuration register storing a programmable value that determines the output characteristic.
U.S. Pat. No. 6,472,747, to Bazarjani, et al., discloses techniques for fabricating analog and digital circuits on separate dies and stacking and integrating the dies within a single package to form a mixed-signal IC that provides many benefits. In one aspect, the analog and digital circuits are implemented on two separate dies using possibly different IC processes suitable for these different types of circuits. The analog and digital dies are thereafter integrated (stacked) and encapsulated within the single package. Bonding pads are provided to interconnect the dies and to connect the dies to external pins. The bonding pads may be located and arranged in a manner to provide the required connectivity while minimizing the amount of die area required to implement the pads.
U.S. Pat. No. 6,605,875, to Eskildsen, discloses an integrated circuit die having bond pads near adjacent sides to allow stacking of dice without regard to dice size. A lower die has keep out areas on its top surface. The keep out areas correspond to two adjacent edges of the lower die. The lower die has bond pads within the keep out areas. An upper die is stacked on the top surface of the lower die such that the bond pads within the keep out areas of the lower die are exposed to accept wire bonds. The configuration of the keep out areas next to adjacent edges of the lower die thus provides flexibility in the design of stacked chip packages because the size of the upper die is not limited by the bond pad configuration of the lower die.
U.S. Pat. No. 6,618,790, to Talreja, et al., discloses a burst transfer operation with a memory device that can be suspended and resumed without having to provide the current memory address when it is resumed. A chip enable signal to the memory device can be deasserted to initiate the suspend operation and place the memory device in a low power standby mode. When the chip enable signal is reasserted, the memory device can be reactivated and the burst transfer can continue where it stopped, without any setup commands. The current address counter and other bus transfer parameters can be saved within the memory device during the suspend operation. When the suspend operation is terminated by reasserting the chip enable signal, the memory device can resume the transfer using the saved parameters.
U.S. Pat. No. 5,778,413, to Stevens, et al., discloses a memory controller that provides a series of queues between the processor and the PCI bus and the memory system. The memory controller is highly programmable for multiple speeds and types of processors and several speeds of memory devices. The memory controller includes a plurality of registers that specify number of clock periods for the particular portions of a conventional dynamic random access memory cycle which are used to control state machine operations.
U.S. Pat. No. 5,768,560, to Lieberman, et al., discloses a dynamically configurable memory system having a programmable controller including a frequency multiplier to maintain memory timing resolution for different bus speeds.
U.S. Pat. Nos. 6,442,076 and 6,657,899, both to Roohparvar, disclose a synchronous flash memory that includes an array of non-volatile memory cells. The memory array is arranged in rows and columns, and can be further arranged in addressable blocks. Data communication connections are used for bi-directional data communication with an external device(s), such as a processor or other memory controller. The memory can write data to one location, such as a memory array block, while data is read from a second location, such as a second memory array block. The memory automatically provides status data when a read command is received for a memory array location that is currently subject to a write operation. The automatic status output allows multiple processors to access the memory device without substantial bus master overhead. The memory can also output status data in response to a status read command.
U.S. Pat. No. 5,369,754, to Fandrich, et al., discloses a flash memory device having a plurality of flash array blocks and a block status register circuit containing a block status register for storing a block status for each flash array block. A flash array controller circuit in the flash memory device performs program or erase operations on the flash array blocks, and maintains the block status in each block status register. An interface circuit in the flash memory device enables read access of the block status registers over a bus.
AM29LV800B is a flash memory device, commercially available from American Micro Devices. It has a parallel interface, with selectable two bus width and a standard status protocol. features a pair of arrays, with flexible sector architectures, and the ability to simultaneous read from one array and program into the other array. Program operation status is conveyed by a status line.
28F640W18 is a single-die firmware hub (FWH) device that includes a flash memory and is commercially available from Intel Corp. It has a synchronous interface bus.
MT48LC4M32B2 is a SDRAM device by Micron Technolgies. Read and write accesses to the memory are burst oriented; accesses start at a selected location and continue for a programmed number of locations. It also features configuration of access time delay and multiple internal banks.
SST25FV is a flash memory device made by Silicon Storage Technology, Inc. It features a serial SPI interface, whose protocol includes a ‘data in’ signal, a ‘data out’ signal, a clock signal, for timing the communication, and a ‘chip select’ signal. The protocol passes commands and address to the device and serially shifts data in or out of the device. Either a single byte or a sequence of data bytes (burst) may be read or written.
In accordance with exemplary embodiments of a fifth aspect of the invention, for the case that the FD is not self timed, the interface enables it to generate its internal timing signals, whatever they are, from the supplied clock signal that serves the synchronous bus; such generation of timing signals is configurable to a wide range of supplied clock frequencies.
Bearing all this in mind, there is provided, according to the third aspect of the invention, a semiconductor die, comprising a plurality of interconnection pads for connecting with a memory die, the two dies packaged together in a stacked manner, wherein the plurality of pads are disposed so that the circuit layout of the semiconductor die is invariable with respect to the size of the memory die, within a given range of sizes.
Similarly there is provided, according to the third aspect of the invention, a memory die, comprising a plurality of interconnection pads for connecting with a semiconductor die, the two dies packaged together in a stacked manner, wherein the plurality of pads are disposed so that the circuit layout of the memory die is invariable with respect to the size of the semiconductor die, within a given range of sizes.
There is further provided, according to the third aspect of the invention, a semiconductor die, comprising a plurality of interconnection pads for connecting with a memory die, the two dies packaged together in a stacked manner and at least two of the pads forming, each, part of a corresponding data line, for carrying data signals between the two dies, wherein the at least two pads are disposed so that the circuit layout of the semiconductor die is invariable with respect to the number of data lines, up to a given maximum number.
Similarly there is further provided, according to the third aspect of the invention, a memory die, comprising a plurality of interconnection pads for connecting with a semiconductor die, the two dies packaged together in a stacked manner and at least two of the pads forming, each, part of a corresponding data line, for carrying data signals between the two dies, wherein the at least two pads are disposed so that the circuit layout of the memory die is invariable with respect to the number of data lines, up to a given maximum number.
According to another feature of the invention, the plurality of pads are disposed along, at most, two mutually adjacent edges of the semiconductor/memory die.
According to further features of the invention, the at least two pads are disposed along a single edge of the die and the data lines are indexed in a sequential order and the disposition along the edge is in the order in which the corresponding data lines are indexed.
According to alternative features of the invention, there is defined a default number of data lines, which is smaller than the given maximum number, wherein a number of the at least two pads, equal to the default number, are disposed along a first edge of the die and all other of the at least two pads are disposed along a second edge, adjacent to the first edge.